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Ascenium Adopts OpenROAD for Energy-Efficient Design Exploration
Ascenium has adopted OpenROAD for architectural exploration and power estimation, enabling early-stage hardware-software tradeoff analysis for their energy-efficient processor designs.
Ascenium has adopted OpenROAD for design exploration and power estimation as part of developing their energy-efficient processor architectures. Energy-efficient chip design starts with the architecture, and OpenROAD enables early-stage analysis that is critical to making informed decisions.
OpenROAD, developed with DARPA MTO funding through the Intelligent Design of Electronic Assets (IDEA) program, offers semiconductor design teams an open-source, no-human-in-loop, 24-hour chip place-and-route solution, reducing barriers related to cost, expertise, and unpredictability inherent in proprietary design solutions.
Open predictive technology models paired with public PDKs enable architects to estimate PPA tradeoffs before detailed design phases. The ASAP7 open-source 7nm FinFET PDK exemplifies this approach, incorporating models for schematic entry, library characterization, synthesis, placement, routing, parasitic extraction, and simulation.
Precision Innovations partnered with Ascenium to support design estimation for their novel low-power processor architecture, enabling reliable hardware-software tradeoff analysis at reduced cost compared to commercial tools.