· News · 1 min read
Energy-Efficient Chip Design Starts with the Architecture
OpenROAD enables early-stage PPA estimation using open predictive technology models and public PDKs, empowering architects to make informed tradeoff decisions before detailed design phases.
OpenROAD, developed with DARPA MTO funding through the Intelligent Design of Electronic Assets (IDEA) program, offers semiconductor design teams an open-source, no-human-in-loop, 24-hour chip place-and-route solution. The platform reduces barriers related to cost, expertise, and unpredictability inherent in proprietary design solutions.
With over 600 tapeouts completed on process nodes down to 12nm, companies increasingly leverage OpenROAD during early-stage hardware and software architectural exploration, where empirical power, performance, and area (PPA) data may not yet exist.
Open predictive technology models paired with public PDKs enable architects to estimate PPA tradeoffs before detailed design phases. The ASAP7 open-source 7nm FinFET PDK exemplifies this approach, incorporating models for schematic entry, library characterization, synthesis, placement, routing, parasitic extraction, and simulation.
Precision Innovations recently partnered with Ascenium to support design estimation for a novel low-power processor architecture, enabling reliable hardware-software tradeoff analysis at reduced cost compared to commercial tools.